There has been conventionally various control methods that in an information processing apparatus that includes a plurality of nodes including processors and memory units, the processors included in the plurality of nodes control synchronization between processes to execute in their hardware threads.
Generally, a thread is the unit of processing of a program to be executed concurrently by software, and multithreading is the concurrent execution of a plurality of threads on one processor.
On the other hand, hardware threading is also known as hardware multithreading, and is referred to as the following technology. For example, hardware threading is a technology for sharing hardware resources such as a functional unit, a register, a TLB (Translation Look-aside Buffer), and a system bus controller on the same core included in a CPU (Central Processing Unit). In other words, hardware threading is a technology for sharing hardware resources to simultaneously operate a plurality of threads on the same core. With regard to hardware threading, known are various implementation methods, such as VMT (Vertical Multi-Threading) and SMT (Simultaneous Multi-Threading), that operate a plurality of threads by time-division multiplexing in addition to the technology for simultaneously operating a plurality of threads.
Considered is, for example, a case where in the above-mentioned hardware threading, a running process in a first hardware thread contained in a first processor included in a first node needs data stored in a second memory unit included in a second node.
As a method of controlling synchronization between processes in the above-mentioned case, there is, for example, a control method in the polling system. In other words, the first processor suspends a running process in the first hardware thread and performs a polling process to access a first memory unit until a process that a second processor included in the second node copies data to the first memory unit is complete. When the process that the second processor copies data to the first memory unit is complete, the first processor reads the data from the first memory unit and resumes the suspended process in the first hardware thread.
Moreover, as another method of controlling synchronization between processes in the above-mentioned case, there is, for example, a control method in an interrupt system. In other words, the first processor suspends a running process in the first hardware thread, and is subsequently given an interrupt notification that notifies that the second processor has completed the process to copy data to the first memory unit. The first processor then executes, as kernel processes of an OS (Operating System), various processes such as a register saving process with the switching of processes, an authorization switching process by the OS, and a process of starting an interrupt handler for reading data from the first memory unit. The first processor then reads the data from the first memory unit to resume the suspended process in the first hardware thread.
Patent Literature 1: Japanese National Publication of International Patent Application No. 2006-500639
Patent Literature 2: Japanese Laid-open Patent Publication No. 2006-031691
However, in the above-mentioned known technologies, although the process is suspended in the first hardware thread, the polling process to access the first memory unit is performed. Therefore, there is a problem that hardware resources shared among a plurality of hardware threads, such as a system bus controller shared among the other hardware threads, are not used effectively in the first processor.
Moreover, in the above-mentioned known technologies, there is a problem that it is not possible to quickly switch processes since kernel processes by the OS such as register saving and restoration processes with the switching of processes to be executed in the first hardware thread incur overhead.